Application scheme of serial port receiving data system based on FPGA device XC2S50 chip

With the rapid development of FPGA and its wide application in modern Electronic design, more and more experiments and designs will use FPGA to communicate with RS232. At the same time, FPGA has the characteristics of powerful functions, small investment in the development process, short cycle, and repeatable programming. The serial receiving function module is integrated on the FPGA chip, which simplifies the circuit, reduces the volume of the circuit board, and improves the reliability. This text mainly introduces the serial receiving module that accords with RS232 standard designed around FPGA.

1 Introduction

With the rapid development of FPGA and its wide application in modern electronic design, more and more experiments and designs will use FPGA to communicate with RS232. At the same time, FPGA has the characteristics of powerful functions, small investment in the development process, short cycle, and repeatable programming. The serial receiving function module is integrated on the FPGA chip, which simplifies the circuit, reduces the volume of the circuit board, and improves the reliability. This text mainly introduces the serial receiving module that accords with RS232 standard designed around FPGA.

2 Principle of asynchronous serial communication

Serial communication is divided into two types: synchronous communication and asynchronous communication. This design adopts the asynchronous communication mode, which is characterized by: the sender and receiver of the communication have independent clocks, and the transmission rate is agreed by both parties. A serial communication baud rate standard series stipulated internationally is: 110, 300, 600, 1200, 1800, 2400, 4800, 9600, 19200, and the unit is bps. This article uses 19200bps.

Asynchronous transfers are character-by-character transfers. The information of a character consists of start bit, data bit, parity bit and stop bit. The transmission of each character is synchronized by the start bit. The front of the character is a start bit. The falling edge is used to notify the receiver that the transmission starts. The data bit is followed by the start bit. At the end, the character itself consists of 5 to 8 data bits. The data bits are followed by a parity bit, followed by a stop bit, which is high, marking the end of a character and preparing for the start of the next character transmission. The stop bit is followed by an idle bit of indeterminate length. Both the stop bit and the idle bit are specified high, which guarantees a falling edge at the beginning of the start bit, as shown in Figure 1. 3 Principle design of hardware interface circuit

In serial communication, the standard RS232-C interface is commonly used. The connection method of the signal pins of the RS232-C interface specifies a 25-core D-type connector DB-25. This design uses a 9-core D-type connector DB-9, and uses the most simple and commonly used three-wire connection. method, that is, the ground, receiving data and sending data are connected with three pins.

Application scheme of serial port receiving data system based on FPGA device XC2S50 chip

The hardware interface circuit diagram of this design is shown in Figure 2, which consists of three parts: FPGA serial port receiving module, MAX232 and DB-9. What FPGA adopts is XC2S50 chip of SPARTAN series of Xilinx Company, its package is TQ144. MAX232CPE of MAXIM Company is designed to meet the standard of EIA/TEA-232E, and has the advantages of low power consumption, high baud rate and low price. The working power supply is +5V, the external capacitance is only luF, and it is a dual-group RS-232 transceiver. MAX232 has two transmitters, only one transmitter is used in this design, and the input end of the other transmitter is grounded and the output end is floating.

The asynchronous data receiving process can be implemented as a whole. The data is input from the RxD terminal of DB-9, and is entered by the RxD terminal of the FPGA serial port receiving module after level conversion through MAX232, and then the received data is judged inside the serial port receiving module. And finally realize the control of the FPGA output signal.

Application scheme of serial port receiving data system based on FPGA device XC2S50 chip

4 Software design of FPGA to receive serial data

The frame format of serial asynchronous communication adopted in this scheme is: 1 start bit + 5 data bits + 1 stop bit. After detection and analysis, if the frame format of asynchronous communication has been determined, then each character can be represented by fixed 7-bit data respectively. For example: character ‘0’: ‘0000011’; character ‘1’: ‘0100011’. The first bit of data ‘0’ is the start bit, the last bit of data ‘1’ is the stop bit, and the middle 5 bits of data are data bits. For example: use the serial port debugging assistant software to send the string ‘100’, the waveform as shown in Figure 3 will be measured on the RxD pin of the FPGA. Among them, st1, st2, st3 represent 3 characters sent successively, and t1, t2, t3 represent 3 states that pass through when each character is detected.

As shown in the waveforms in Figure 3, the receive logic first checks for the start bit by detecting the falling edge of the incoming data. Then generate a receive clock, and use the receive clock to sample the serial input data. Since the characters ‘0’ and ‘1’ differ only in the first bit of the 5-bit data bits, the string sent by the serial debugging assistant can be obtained as long as the first bit of data is accurately detected. Then use the shift operation to store the string in a buffer (ie, another set of strings that can be updated).

Application scheme of serial port receiving data system based on FPGA device XC2S50 chip

As for the remaining 4 data bits and one stop bit, they can not be sampled with the receiving clock. After all the strings sent by the serial port debugging team are stored, they will be judged in this module together, and different outputs of the FPGA will be controlled according to the different strings. The receive clock is generated according to the baud rate of data transmission: receive clock = 16×19200Hz. It starts with the falling edge of the start bit and ends with the rising edge of the 5th data bit. The following is the VHDL source program that implements the detection of the first character.

if (clk0’event and clk0=’1′) then — external clock

case state is

when st1=” — the first character starts

case state is

when t1=》 ——Start bit starts

if (rxd=’1′) then — not counting until the falling edge

cnt16 “= “0000”;

cnt48 “= “000000”; —All clocks are cleared

else cnt16 “=cnt16+1; — the falling edge, the start bit count starts

end if;

if (cnt16=”1111″) then

tate <= t2; --- After the start bit is finished, enter the data bit

end if;

when t2=》 —— enter the first data bit

if (cnt16=”1111″) then

cnt16 “= “0000”;

else cnt16 “= cnt16+1;

end if;

if (cnt16=”0011″) then

sdata <= rxd; -- sample the first data bit

end if;

if (cnt16=”0111″) then

if(sdata=’0′)then

data(0) “=’0′;

else data (0) “=’1′; — judge the sampling value, if it is 0, the sent character is 0,

vice versa

end if;

end if;

if (cnt16=”1111″) then

tate <= t3; ——The first bit of data is finished, enter the next state

end if;

when t3=》 ——Enter the 2nd, 3rd and 4th data status

if (cnt16=”1111″) then

cnt48 “= “000000”;

else cnt48 “= cnt48+1; —Do not sample the remaining data, count directly

end if;

if (cnt48=”101111″) then

sdata “=’0′; —Sampling bit is cleared

tate <= t1; --- enter the ready state to collect the next character

state <= st2; --- After the first character is collected, enter the next character

end if;

end case;

fdata(0) <= data(0); ——The collected characters are stored in the buffer area

………………

The acquisition process for each character is the same. According to the actual needs, the author only allows the computer to send 3 binary characters, which can control the 8 output states of the FPGA. After the entire VHDL source program is written, use Modelsim 6.0 to simulate, as shown in Figure 4.

Application scheme of serial port receiving data system based on FPGA device XC2S50 chip

In view of the special relationship between the transmitted character and its asynchronous transmission frame format, the rxd in this simulation is replaced by a waveform with a period of 16×clk0, so the string ‘111’ is received. The serial port debugging assistant needs to send a set of strings at regular intervals (greater than 1ms), so the waiting state st4 is necessary, and it is also the preparation state for receiving the next character. The buffer is an empty 3-bit array fdata that must be cleared before receiving the next character.

5 Conclusion

Although the slow speed of serial communication has become more and more obvious, because of its few transmission lines and low cost, serial communication will continue to be used in the development of most electronic products. The serial receiver module introduced in this paper is designed by the author according to the experimental requirements, and the computer has successfully completed the accurate control of the FPGA in the experiment. Therefore, this article can also be used as an example for developers to communicate.

Author: Yoyokuo