Wireless TEMs (Telecom Equipment Manufacturers) are under pressure to deploy base station architectures that are built, deployed and operated with smaller footprint, lower power consumption, and lower manufacturing costs. A key strategy to achieve this is to separate the RF receiver and power amplifier from the base station and use them to directly drive their respective antennas. This is called Remote Radio Technology (RRH). The baseband data is transmitted back to the base station via a SERDES-based public radio interface (CPRI). This article focuses on specific low-latency variation design ideas, implemented on a low-cost FPGA using embedded SERDES transceivers and a CPRI IP (intellectual property) core.
Deployment of RRH
The advantages of separating the radio frequency (RF) transceiver and power amplifier from the “Hotel” base station have been well written, as shown in Figure 1. But the most striking is the RRH’s advantages in terms of power consumption, flexible deployment, small fixed size, and overall low cost.
Figure 1 Remote Radio Technology (RRH) solution
As the RRH is dispersed from the base station, the operator must ensure that the system delay between the radio head and the hotel BTS can be calibrated, because the delay information is used for system calibration, and the overall round-trip delay must be minimized. With concatenated RRHs, each RRH hop variation is added, so this requirement increases accordingly, for one-way and round-trip, the CPRI specification handles the accuracy of the timing of these links.
FPGA Implementation for Low Latency Variation
Figure 2 shows the existing major functional blocks in a traditional SERDES/PCS implementation, with the highlighted parts highlighting the major parts that cause delay variations (such as the RX path shown in the example)
Figure 2 Traditional CPRI receiver implementation
The delay variation comes from several elements, such as the analog SERDES and digital PCS logic, as well as the actual soft IP itself. Analog SERDES have relatively tight timing; however, word alignment and bridge FIFOs are the two main contributors to large delay variations. Before proposing a solution, it is important to understand why word alignment and bridge FIFOs have such a large impact. As shown in Figure 3, the word-alignment function can result in a delay variation of up to 9-bit cycles, depending on the initial position of the word-aligned pointer within a 10-bit cycle. If the 10-bit sampling window captures the alignment characters well, such as a) in Figure 3, there is no delay. However, if the sampling window is not aligned with the character, this results in a delay of up to 9 bit periods, as shown in b) in Figure 3.
Figure 3 Delay variation of word alignment
Second, with a SERDES-based FPGA hybrid structure, a bridge FIFO (Figure 4) is also required to support the transition of the clock domain, which can introduce up to 2 parallel clock cycles of delay variation from the high-speed PCS clock to the FPGA clock domain. At a rate of 2.488Gbps, the PCS clock runs at one-tenth of the rate, which produces a clock cycle of about 4ns. Therefore, it can be seen that there is a worst case variation of +/-8ns in each direction of the FIFO (Tx & Rx), resulting in a total variation of +/-16ns.
Figure 4 Delay variation due to bridge FIFO
The situation is even worse when the designer doesn’t see these delay changes. Because they need to be compensated at the system level to support multiple Tx and GPS services.
Table 1 compares the delay variation to the CPRI specification (section 3.5). It can be clearly seen that word alignment and bridge FIFOs play a major role in large delay variations, resulting in round trip delay tolerances that exceed the CPRI specification.
Table 1 components with delay changes in the original design
Once the problem is identified, minor modifications can be made. In some implementations, the delay information measured by word alignment in PCS can be obtained by accessing registers, which can bypass the clock domain FIFO and implement it with FPGA logic, which can compensate for delay changes at the system level. Figure 5 illustrates a low-latency design with compensable critical delay variations.
Figure 5 Low latency implementation
Now to summarize, when using the proposed implementation, the elements causing large delay variations disappear, and system-level compensation can be utilized to ensure the expected delay during transmission. Of course analog SERDES and IP, or customer designs still have delays, but the overall accuracy has been greatly improved and can now be used in multi-hop applications. Table 2 illustrates the new delay changes in this configuration. The timing now meets the round-trip CPRI delay specification, which is short enough for applications that support multiple hops.
Table 2 Latency variation in low latency implementation
Some additional advantages of using FPGA
FPGAs have been part of the wireless industry’s success for many years. From simple glue logic functions to more complex functions such as digital upconversion, digital downconversion, crest factor attenuation, and digital predistortion required in today’s RRH designs, leveraging the flexibility of FPGAs and the fast time-to-market advantage. Features that support the CPRI interconnect, such as embedded DSP blocks, embedded memory, and high-speed serial I/O (SERDES), are perfectly aligned with the new demands of wireless equipment vendors. Now base station designers can integrate system-level functions on low-cost, low-power programmable platforms such as the Lattice ECP3 FPGA.
Remote base station topologies offer system providers many advantages, and FPGAs are ideal for fulfilling these needs. Therefore, using a programmable, low-power, low-cost mid-range FPGA solution is the best approach for next-generation BTS development.